Memory reliability is an important issue. This is particularly (but not exclusively) true of flash memory devices and especially NAND flash memory which is becoming a rapidly more popular form of solid-state memory for use in portable and/or consumer applications.
This popularity can be attributed to NAND flash's fast decline in price per unit storage over the past years, making it very competitive compared to more established media such as tape, compact discs and magnetic hard disk drives. In addition, it is more shock resistant than CDs or hard drives (flash memory requires no moving parts), more compact (smaller form factor), more systemically consistent with the rest of the solid-state device, and requires lower power.
NOR memory doesn't normally contain manufacture time errors, but is typically more expensive and less dense than other memory technologies such as NAND which unfortunately do have error management issues.
As illustrated schematically in FIG. 1, memories such as NAND flash devices are divided into a plurality of areas in the form of blocks 2, each block 2 being divided into a plurality of pages 4. FIG. 1 shows four such blocks 2a-2d contiguous in address space, but it will be appreciated that there will typically be many more blocks and also that the figure is schematic such that the blocks are not necessarily physically arranged like this on the chip. For simplicity only block 2a is illustrated as being divided pages 4, but each other block 2 is also divided into pages and the number of pages shown is again schematic.
Reading of the memory is performed on a per-page basis. Writing involves erasing on a per-block basis then programming pages within that block. This has manufacturer or device specific issues. For example, some manufacturers say that following erase, pages within the block should be programmed in sequential order, etc. Others don't mention ordering issues but suggest that all pages in a block must be programmed before other operations are performed to increase the block's lifetime.
If any page within a block is “bad” then the block should be considered bad and should not be used. Some blocks can be bad on manufacture, and are tagged as such by the manufacturer in a particular page of each bad block. “Bad” means at least one page within the block has at least one byte which is known to not read reliably. Also, some manufacturers say that writing to bad blocks can actually cause other blocks to fail.
Errors may also develop at a later date, after manufacture. For example, NAND flash memory experiences “write disturbance” whereby it wears out when erased and programmed too many times (as mentioned, a write is a combination of erasing a block and then programming one or more pages). Techniques to correct or compensate for such wear are known in the art, for example flash file system software using erase/program wear-levelling. Further, random radiation errors may occur for example when a cosmic ray or alpha particle passes through a memory cell causing a bit to change from logic-one to a logic-zero or vice-versa. Again, techniques for coping with such errors are known.
The errors in question may be hard errors or soft errors. Soft errors are errors whereby the cell in which the error occurs can be rewritten, and hard errors are errors which cause a cell to be permanently bad.
A number of techniques also exist for initially detecting errors. These include the use of error correction codes (ECCs), cyclic redundancy checks (CRCs), and parity checks. Details of such techniques will be familiar to a person skilled in the art.
Nonetheless, there is still scope to improve the reliability of memory devices.
Aside from errors such as write-disturbance errors or random errors, the lifetime of a memory device may also be limited by the effect of read disturbance due to too many reads. However, there is currently very little awareness of this problem in the art, with manufacturers' data sheets giving no concrete data about the extent of the problem. Accordingly, it is not surprising that little if anything has currently been done to consider how, when or in what circumstances read disturbance should be addressed. In fact, the problem is generally ignored, which could be the cause of many unexplained failures in a wide range of devices.